University of Ottawa, Ottawa
PhD of Computer Science
2007-2009      BeiHang University, Beijing     Master of Computer Architecture in Computer Science
2003-2007      BeiHang University, Beijing     Undergraduate Degree in Computer Science
Samsung Electronics, Beijing
2009-2012        Space Star Co. Ltd, Beijing     FPGA Engineer
A high-speed parallel architecture for RS decoding
Link for this work
2012      CN 102361460A      A high-speed parallel architecture for Viterbi decoding Link for this work
2013      CN 102708012B      A fault-tolerant and parallel computing system of satellite Link for this work
2014      CN 103678206A      A remote sensing data processing system based on FPGA Link for this work
Qian Cui, Guy-Vincent Jourdan, Gregor v. Bochmann, Russell Couturier, Iosif-Viorel Onut.
Tracking Phishing Attacks Over Time.
26th International World Wide Web Conference(WWW '17), 2017
Qian Cui, Xiaopeng Gao, Xiang Long. Design and Implementation of PCI Express DMA Controller Based on Weighted Round Robin Policy (in Chinese) .Microcomputer Information, 2010, 26(23):147-149.
Zhe Zhang, Qian Cui, Xiaopeng Gao, Xiang Long. Network Application for Multi-Core Architecture (in Chinese) .Microelectronics & Computer, 2007, 24(10):39-42.
Over 50,000 Lines:
Over 10,000 Lines: Verilog/Java
Phishing sites detection
· Various crawlers to fetch information of sites, such whois, DOM,etc.
· Use clustering and machine learning to detect phishing sites
· All the works are done by Python
Web crawler and web robot based on Python
· A Web crawler to extract all the blogs and images in RenRen(Chinese Facebook) for any authorized account
· Some web robots to help me deal flash sale and other misc things
· Optimize the parallel performance for the crawler
wiGig wireless Linux driver and software architecture
· Optimize cache access efficiency during DMA operation
· Optimize DMA operation by pipelined DMA ring
· Optimize socket transmission for jumbo frames
· Get final throughput: 3.0Gbps in UDP, 2.5Gbps in TCP. Link for this work
Kernel porting and power optimization for Samsung Exynos 5410 chip (four A15 cores and four A7 cores)
· Port kernel and uboot to Exynos 5410 chip
· Analyse and optimize network performance with a thread monitoring the net throughput to choose different mechanisms
High-Speed prototype system based on PCI/PCI-E bus
· See the hardware section
Optimization Viterbi and RS decoding algorithm
· Implement Viterbi decoding parallel architecture based on Ping- Pong buffering strategy
· Implement RS decoding parallel architecture based on interleaving dividing strategy
863 project “Reconstruction Accelerator”
· Design a duplex mode memory controller based on fair schedule strategy
· Design a parallel architecture for PSDM (Prestack Depth Migration) algorithm
Wormhole Router on SOC
· Design a new network modeling tool DClick for network on chip
Here are some my hardware designs when I was an FPGA engineer ^_^
My wife and I are keen to travelling and photography, here are some big gains during our tours.
If you want to learn more about me, you can download my CV .